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											2018-01-21 10:33:32 -05:00
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							|  |  |  | <h2>VHDL mode</h2> | 
					
						
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							|  |  |  | <div><textarea id="code" name="code"> | 
					
						
							|  |  |  | LIBRARY ieee; | 
					
						
							|  |  |  | USE ieee.std_logic_1164.ALL; | 
					
						
							|  |  |  | USE ieee.numeric_std.ALL; | 
					
						
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							|  |  |  | ENTITY tb IS | 
					
						
							|  |  |  | END tb; | 
					
						
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							|  |  |  | ARCHITECTURE behavior OF tb IS | 
					
						
							|  |  |  |    --Inputs | 
					
						
							|  |  |  |    signal a : unsigned(2 downto 0) := (others => '0'); | 
					
						
							|  |  |  |    signal b : unsigned(2 downto 0) := (others => '0'); | 
					
						
							|  |  |  |     --Outputs | 
					
						
							|  |  |  |    signal a_eq_b : std_logic; | 
					
						
							|  |  |  |    signal a_le_b : std_logic; | 
					
						
							|  |  |  |    signal a_gt_b : std_logic; | 
					
						
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							|  |  |  |     signal i,j : integer; | 
					
						
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							|  |  |  | BEGIN | 
					
						
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							|  |  |  |     -- Instantiate the Unit Under Test (UUT) | 
					
						
							|  |  |  |    uut: entity work.comparator PORT MAP ( | 
					
						
							|  |  |  |           a => a, | 
					
						
							|  |  |  |           b => b, | 
					
						
							|  |  |  |           a_eq_b => a_eq_b, | 
					
						
							|  |  |  |           a_le_b => a_le_b, | 
					
						
							|  |  |  |           a_gt_b => a_gt_b | 
					
						
							|  |  |  |         ); | 
					
						
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							|  |  |  |    -- Stimulus process | 
					
						
							|  |  |  |    stim_proc: process | 
					
						
							|  |  |  |    begin | 
					
						
							|  |  |  |         for i in 0 to 8 loop | 
					
						
							|  |  |  |             for j in 0 to 8 loop | 
					
						
							|  |  |  |                 a <= to_unsigned(i,3); --integer to unsigned type conversion | 
					
						
							|  |  |  |                 b <= to_unsigned(j,3); | 
					
						
							|  |  |  |                 wait for 10 ns; | 
					
						
							|  |  |  |             end loop; | 
					
						
							|  |  |  |         end loop; | 
					
						
							|  |  |  |    end process; | 
					
						
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							|  |  |  | END; | 
					
						
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							|  |  |  | <p> | 
					
						
							|  |  |  | Syntax highlighting and indentation for the VHDL language. | 
					
						
							|  |  |  | <h2>Configuration options:</h2> | 
					
						
							|  |  |  |   <ul> | 
					
						
							|  |  |  |     <li><strong>atoms</strong> - List of atom words. Default: "null"</li> | 
					
						
							|  |  |  |     <li><strong>hooks</strong> - List of meta hooks. Default: ["`", "$"]</li> | 
					
						
							|  |  |  |     <li><strong>multiLineStrings</strong> - Whether multi-line strings are accepted. Default: false</li> | 
					
						
							|  |  |  |   </ul> | 
					
						
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							|  |  |  | <p><strong>MIME types defined:</strong> <code>text/x-vhdl</code>.</p> | 
					
						
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